Current Job Openings
If you’re interested or would like more information, please send your resume to hr@paradetech.com.
San Jose, California
Accountant
Annual base salary: $55,000 – $74,000
We’re seeking a self-motivated individual with high attention to detail who’s looking to grow their career in accounting.
Responsibilities
- Validate accuracy and completeness of vendors information the accounting system and bank platform.
- Ensure timeliness, accuracy, completeness, approval, coding, data entry, scanning/processing of operating expenses, including validation of electronically filed invoices to AP system.
- Follow up on Accounts Payable aging and payment analysis by weekly and set up payments (ACH and Wires) and send them for approval.
- Responsible for intercompany billing.
- Responsible for various bank accounts transactions.
- Responsible for some of Parade Cayman vendors month-end account reconciliations.
- Code invoices and other records to maintain organized and accurate records.
- Assist with certain vendors’ purchase requisition form process and issue purchase order in D365.
- Collaborate internally with team members across multiple departments and vendors to ensure accurate and timely payments.
- Support month-end close process and filing and document organization.
- Assist with Parade Internal Control audit requests, Auditors’ quarter-end review, semi-year audit and year-end audit related requests.
Required Qualifications
- Bachelor’s degree in Accounting, Business Administration, or related field.
- At least 2 years of relevant work experience.
- Strong Excel knowledge.
- Microsoft Dynamics (D365) experience is preferred.
- English proficiency required; Mandarin is a plus.
San Jose, CA or Beaverton, Oregon
Quality and Reliability Assurance Manager, Operations
Annual base salary: $150,000 – $190,000
We’re seeking an experienced Quality and Reliability Assurance Manager to own product reliability and quality from development through production, ensuring our products meet industry standards, customer expectations, and long-term performance requirements.
Key Responsibilities
- Generate reliability metrics, statistical modeling, and lifetime estimations for new products.
- Prepare specialized reliability reports tailored to meet the unique requirements of specific customers.
- Lead product qualification efforts, including AEC-Q100, ISO 9001, and customer-specific requirements.
- Coordinate engineering builds, establishing initial templates for new engineering builds (NPI).
- Interface with subcontractors and vendors to ensure compliance with reliability and quality standards.
- Manage customer QA requests.
- Host weekly MRB review meeting.
Required Qualifications
- Master’s degree or above in Electrical Engineering, Physics, or semiconductor-related field.
- Familiarity with IC reliability modeling for various tests, like HTOL, HCI, NBTI, PBTI, EM, etc.
- Strong understanding of reliability testing methodologies and statistical analysis.
- Familiarity with industry standards such as AEC-Q100, JEDEC JESD47, ISO 9001.
- Excellent communication skills to effectively convey complex technical concepts.
- Experienced with FA tools, knowledge of reliability software.
- Familiar with automotive reliability requirements.
- Bilingual in English and Mandarin Chinese is strongly preferred.
Beaverton, Oregon
Application Engineer
Annual base salary: $100,000 – $180,000
Responsibilities:
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Lead hardware bring-up, ASIC prototyping, IC validation, and customer technical support.
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Certify new products and represent Parade at USB, PCIe, and VESA workshops.
Qualifications:
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Must have a Bachelor’s degree and more than 3 years of relevant experience.
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Have experience debugging hardware and software in a lab environment and understand the ASIC design cycle from specification to working silicon.
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Ability to work on very challenging tasks and meet customer’s deadlines.
Required Experience:
- Design and/or review engineering and customer board schematics.
- Working knowledge of Orcad and Allegro development tools.
- Ability to use Xilinx FPGA tools for implementing an ASIC design for at-speed prototyping. Must be familiar with Chipscope to help in the ASIC prototype debugging cycle.
- Ability to do board bring-up and debug.
- Write technical documents such as application notes and user guides.
- Characterize and test new ICs.
- Knowledge of high and low speed serial protocols (USB3/2, PCIe, SPI, I2C, etc.).
- Experience with USB and PCIe protocol analyzers is a plus.
- Ability to read specifications and implement test procedures.
- Work with customers and partners to design in our chips and solve technical issues.
- Familiarity with the USB, PCIe, and/or Display Port certification process is a plus.
Staff ASIC Design Engineer
Annual base salary: $150,000 – $180,000
Responsibilities:
- SOC subsystem architect including documentation of micro-architecture
- Lead design team for major subsystems of large SOCs
Qualifications:
- BS/MS degree with 10+ years of relevant work experience
- Expert understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least two prior RTL designs
- Extensive knowledge of PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
Sr. ASIC Design Engineer
Annual base salary: $120,000 – $150,000
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree with 5+ years of relevant work experience
- Good understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least one prior RTL designs
- Familiarity with PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
ASIC Design Engineer
Annual base salary: $90,000 – $120,000
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree and 0-5 years of work experience
- Good understanding of digital design and verification practices from course work or job experience
- Ability to write Verilog RTL and basic knowledge or experience with simulations
- Familiarity with high-speed protocols such as USB3 or PCIe is a desirable
Required Experience:
- Demonstrate a basic knowledge of System Verilog (SV) or similar verification language
- Demonstrate a basic knowledge of Verilog for chip design and verification
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Relevant course work for VLSI/ASIC design
Taipei & Hsinchu
Sr./ Analog Design Engineer
Sr./ Logic Design Engineer
Nanjing
Sr./ Analog Design Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Software Engineer
Sr./ System Engineer
Shanghai
Sr./ Analog Design Engineer
Sr./ FAE Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Product Engineer
Sr./ Software Engineer
Sr./ System Validation Engineer
Sr./ System Engineer
Sr./ Test Engineer
For any questions or further information, contact hr@paradetech.com