Current Job Openings
For information, contact hr@paradetech.com
Send resume to: Parade Technologies, Inc. 2720 Orchard Pkwy, San Jose, CA 95134
San Jose, California
Accountant
Annual base salary: $55,000 – $74,000
We’re seeking a self-motivated individual with high attention to detail who’s looking to grow their career in accounting.
Responsibilities
- Validate accuracy and completeness of vendors information the accounting system and bank platform.
- Ensure timeliness, accuracy, completeness, approval, coding, data entry, scanning/processing of operating expenses, including validation of electronically filed invoices to AP system.
- Follow up on Accounts Payable aging and payment analysis by weekly and set up payments (ACH and Wires) and send them for approval.
- Responsible for intercompany billing.
- Responsible for various bank accounts transactions.
- Responsible for some of Parade Cayman vendors month-end account reconciliations.
- Code invoices and other records to maintain organized and accurate records.
- Assist with certain vendors’ purchase requisition form process and issue purchase order in D365.
- Collaborate internally with team members across multiple departments and vendors to ensure accurate and timely payments.
- Support month-end close process and filing and document organization.
- Assist with Parade Internal Control audit requests, Auditors’ quarter-end review, semi-year audit and year-end audit related requests.
Required Qualifications
- Bachelor’s degree in Accounting, Business Administration, or related field.
- At least 2 years of relevant work experience.
- Strong Excel knowledge.
- Microsoft Dynamics (D365) experience is preferred.
- English proficiency required; Mandarin is a plus.
Beaverton, Oregon
Staff ASIC Design Engineer
Responsibilities:
- SOC subsystem architect including documentation of micro-architecture
- Lead design team for major subsystems of large SOCs
Qualifications:
- BS/MS degree with 10+ years of relevant work experience
- Expert understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least two prior RTL designs
- Extensive knowledge of PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
Sr. ASIC Design Engineer
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree with 5+ years of relevant work experience
- Good understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least one prior RTL designs
- Familiarity with PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
ASIC Design Engineer
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree and 0-5 years of work experience
- Good understanding of digital design and verification practices from course work or job experience
- Ability to write Verilog RTL and basic knowledge or experience with simulations
- Familiarity with high-speed protocols such as USB3 or PCIe is a desirable
Required Experience:
- Demonstrate a basic knowledge of System Verilog (SV) or similar verification language
- Demonstrate a basic knowledge of Verilog for chip design and verification
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Relevant course work for VLSI/ASIC design
Taipei & Hsinchu
Sr./ Analog Design Engineer
Sr./ Logic Design Engineer
Nanjing
Sr./ Analog Design Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Software Engineer
Sr./ System Engineer
Shanghai
Sr./ Analog Design Engineer
Sr./ FAE Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Product Engineer
Sr./ Software Engineer
Sr./ System Validation Engineer
Sr./ System Engineer
Sr./ Test Engineer
For any questions or further information, contact hr@paradetech.com