Current Job Openings
If you’re interested or would like more information, please send your resume to hr@paradetech.com.
San Jose, California
Dynamics 365 F&O Administrator
Annual base salary: $110,000 – $145,000
In this role, you’ll be part of our IT team and own the day-to-day health of our Microsoft Dynamics 365 Finance & Operations environment and the business automations built around it, partnering directly with stakeholders across Finance, Sales, Customer Service, and Manufacturing.
Responsibilities
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Administer and support D365 F&O users and business processes across Finance, Customer Service, Sales, Planning, Inventory, and Manufacturing.
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Manage user accounts, roles, security permissions, service accounts, and Microsoft Entra application mappings, applying least-privilege principles throughout.
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Diagnose and resolve issues across workflows, batch jobs, Data Management imports and exports, recurring integrations, OData access, and environment refreshes.
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Monitor production automations, investigate incidents, drive recovery, and rotate credentials on schedule.
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Support and extend the Customer Service sales-order and Planning production-order automations built on SharePoint, Power Automate, Azure Functions, Python, Excel, and D365.
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Maintain the logic that keeps those automations reliable — field mappings, input validation, master-data checks, duplicate prevention, post-transaction verification, notifications, and exception handling.
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Work with D365 data entities, custom services, and X++ changes; manage reference-data exports and integrations with bills of materials, routes, warehouses, and source lots.
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Prepare test data and run unit, regression, and user-acceptance testing across test and production environments.
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Manage source control and Azure DevOps builds, and coordinate D365 deployments.
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Document system configurations, architecture, mappings, operating procedures, and troubleshooting steps.
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Provide user guidance and partner with cross-functional teams to turn business needs into working solutions.
Required Qualifications
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2–5 years of hands-on experience with ERP administration, enterprise applications, systems integration, or software development. Substantial internship and project work counts toward the lower end of this range.
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Working knowledge of D365 F&O in at least two of the following: security and role configuration, Data Management, workflows, batch jobs, OData entities, or Microsoft Entra application mappings.
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Bachelor’s degree in Computer Science, Information Systems, or a related field — or equivalent practical experience.
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Relational database fundamentals — SQL queries, tables, relationships, mappings, and normalization.
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Practical scripting ability in Python or a comparable language used for data processing and automation.
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Integration fundamentals — REST APIs, JSON, authentication, and service-to-service integrations.
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Advanced Excel skills, with the ability to validate, transform, and reconcile structured business data.
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Strong analytical and troubleshooting skills, with clear written and verbal communication.
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Ability to learn independently, document your work carefully, and collaborate across business and technical teams.
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Effective, accountable use of AI tools for research, coding, testing, debugging, documentation, and process automation while independently validating accuracy, security, and business requirements.
Beaverton, Oregon
Application Engineer
Annual base salary: $100,000 – $180,000
Responsibilities:
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Lead hardware bring-up, ASIC prototyping, IC validation, and customer technical support.
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Certify new products and represent Parade at USB, PCIe, and VESA workshops.
Qualifications:
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Must have a Bachelor’s degree and more than 3 years of relevant experience.
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Have experience debugging hardware and software in a lab environment and understand the ASIC design cycle from specification to working silicon.
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Ability to work on very challenging tasks and meet customer’s deadlines.
Required Experience:
- Design and/or review engineering and customer board schematics.
- Working knowledge of Orcad and Allegro development tools.
- Ability to use Xilinx FPGA tools for implementing an ASIC design for at-speed prototyping. Must be familiar with Chipscope to help in the ASIC prototype debugging cycle.
- Ability to do board bring-up and debug.
- Write technical documents such as application notes and user guides.
- Characterize and test new ICs.
- Knowledge of high and low speed serial protocols (USB3/2, PCIe, SPI, I2C, etc.).
- Experience with USB and PCIe protocol analyzers is a plus.
- Ability to read specifications and implement test procedures.
- Work with customers and partners to design in our chips and solve technical issues.
- Familiarity with the USB, PCIe, and/or Display Port certification process is a plus.
Staff ASIC Design Engineer
Annual base salary: $150,000 – $180,000
Responsibilities:
- SOC subsystem architect including documentation of micro-architecture
- Lead design team for major subsystems of large SOCs
Qualifications:
- BS/MS degree with 10+ years of relevant work experience
- Expert understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least two prior RTL designs
- Extensive knowledge of PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
Sr. ASIC Design Engineer
Annual base salary: $110,000 – $150,000
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree with 5+ years of relevant work experience
- Good understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least one prior RTL designs
- Familiarity with PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
ASIC Design Engineer
Annual base salary: $75,000 – $110,000
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree and 0-5 years of work experience
- Good understanding of digital design and verification practices from course work or job experience
- Ability to write Verilog RTL and basic knowledge or experience with simulations
- Familiarity with high-speed protocols such as USB3 or PCIe is a desirable
Required Experience:
- Demonstrate a basic knowledge of System Verilog (SV) or similar verification language
- Demonstrate a basic knowledge of Verilog for chip design and verification
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Relevant course work for VLSI/ASIC design
Taipei & Hsinchu
Sr./ Analog Design Engineer
Sr./ Logic Design Engineer
Nanjing
Sr./ Analog Design Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Software Engineer
Sr./ System Engineer
Shanghai
Sr./ Analog Design Engineer
Sr./ FAE Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Product Engineer
Sr./ Software Engineer
Sr./ System Validation Engineer
Sr./ System Engineer
Sr./ Test Engineer
For any questions or further information, contact hr@paradetech.com