Current Job Openings
For information, contact hr@paradetech.com
Send resume to: Parade Technologies, Inc. 2720 Orchard Pkwy, San Jose, CA 95134
Beaverton, Oregon
Staff ASIC Design Engineer
Responsibilities:
- SOC subsystem architect including documentation of micro-architecture
- Lead design team for major subsystems of large SOCs
Qualifications:
- BS/MS degree with 10+ years of relevant work experience
- Expert understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least two prior RTL designs
- Extensive knowledge of PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
Sr. ASIC Design Engineer
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree with 5+ years of relevant work experience
- Good understanding of digital design and verification practices
- Ability to write RTL based on a specification and simulate vectors to verify RTL
- Experience using System Verilog (SV) and at least one prior RTL designs
- Familiarity with PCIe, USB3, or Power Delivery
Required Experience:
- Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
- Demonstrate an expert knowledge of Verilog for chip design and verification
- Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, first silicon bring up and debug
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Experience with creating module level test benches and BFMs
ASIC Design Engineer
Responsibilities:
- Member of design team for large SOCs
Qualifications:
- BS/MS degree and 0-5 years of work experience
- Good understanding of digital design and verification practices from course work or job experience
- Ability to write Verilog RTL and basic knowledge or experience with simulations
- Familiarity with high-speed protocols such as USB3 or PCIe is a desirable
Required Experience:
- Demonstrate a basic knowledge of System Verilog (SV) or similar verification language
- Demonstrate a basic knowledge of Verilog for chip design and verification
- Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
- Relevant course work for VLSI/ASIC design
Taipei & Hsinchu
Sr./ Analog Design Engineer
Sr./ Logic Design Engineer
Nanjing
Sr./ Analog Design Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Software Engineer
Sr./ System Engineer
Shanghai
Sr./ Analog Design Engineer
Sr./ FAE Engineer
Sr./ Layout Designer Engineer
Sr./ Logic Design Engineer
Sr./ Product Engineer
Sr./ Software Engineer
Sr./ System Validation Engineer
Sr./ System Engineer
Sr./ Test Engineer
For any questions or further information, contact hr@paradetech.com