DP691 – 4 Lane eDP 1.4b PSR2 Tcon

eDP v1.4b LCD Timing Controller with PSR2 and Integrated Frame Buffer, Up To 2560×1700 Resolution

DP691 supports the PSR2 protocol in the Embedded DisplayPort Standard version 1.4b.  The device enables a new level of power reduction by supporting all eDP 1.4b power saving features including PSR2 with Selective Update, Advanced Link Power Management (ALPM), and VESA Display Stream Compression (DSC).

DP691 block-3


  • Supports display resolutions up to 2560×1700
  • Compliant to VESA Embedded DisplayPort Standard version 1.4b
  • Supports PSR and PSR2 with Selective Update
  • Supports VESA Display Stream Compression (DSC) v1.1
  • Includes backlight control through AUX
  • 1.62 and 2.7Gbps eDP link operation with 1, 2, or 4 lanes
  • CrystalFree™ technology; no external clock reference required
  • Supports full and fast link training, and no link training
  • Up to 24 color bit depth RGB format eDP input
  • 6 or 8 component bit depth point-to-point SOC panel interface
  • Media optimized playback modes
  • Color Engine, FRC, and Gamma Correction with EEPROM for LUT storage
  • Media optimized playback modes
  • Programmable BIST and aging patterns
  • Parade’s exclusive Smart-Backlight™ dynamic backlight control for color and power optimization
  • Supports DisplayPort™ standard SSC 0.5% down spreading and additional spreading on Source Driver interface
  • Supports VESA Adaptive-Sync
  • Supports eDP DRR/nvDPS/sDRRS power saving modes
  • ASSR display authentication support
  • ESD HBM 8kV
  • 5x12mm QFN RoHs Halogen free package


  • High-Resolution COG LCD Panels for Mobile PC and AIO platforms