Direct Drive LCD Timing Controller with DisplayPort™ Receiver

The VESA® DisplayPort display interface specification leverages matured technologies such as the physical layer of PCI Express®, packet based transactions and quality of service of data communications, and advanced CMOS semiconductor process to address existing and future growth of digital displays on PC and consumer electronics applications. DP621, an LCD Timing controller with DisplayPort Receiver, provides a scalable and interoperable digital display interface together with a programmable timing control scheme to address broad applications on PC and embedded display devices.

Key Features

  • DisplayPort Receiver compliant with DisplayPort Specification 1.1a for both 1.62 and 2.7 Gbps
  • Very low power consumption, 255mW to 430mW to support up to WUXGA
  • No crystal or external reference clock needed with Parade’s CrystalFree technology
  • Built-in adaptive equalization to support 2.7 Gbps transmission over minimal 15m AWG28 cable without requesting transmitter pre-emphasis
  • Excellent ESD performances; HBM 8kV at connector pins and 5kV all other pins
  • Supports DisplayPort 1 or 2 lanes operation
  • Supports additional Spread Spectrum Clocking on DisplayPort Receiver, RSDS/mini-LVDS transmitter to reduce EMI
  • Supports 18/24-bit RGB color format
  • HDCP 1.3 for Content Protection, Integrated HDCP key ROM
  • On-chip microprocessor with SPI ROM interface
  • Supports various LCD panel timing including WUXGA (1920×1200), UXGA (1600×1200), WSXGA+ (1680×1050), SXGA+ (1440×1050), SXGA (1280×1024), WXGA+ (1440×900) and WXGA (1280×800, or 1360×768, or 1280×768)
  • Supports reduced blanking, reduced refresh rate and dynamic refresh rate timing mode
  • Programmable TCON control signal generation and programmable FRC patterns
  • 6-bit, single RSDS or dual RSDS output, maximum clock rate of 90MHz (for WUXGA)
  • 6 or 8-bit, dual mini-LVDS output, maximum clock rate of 162MHz (for WUXGA)
  • Supports asymmetrical configuration with 3:4 left-right ratio in the number of column drivers by selecting output clock frequency from the video clock frequency of 5, 10, 15, 25%
  • Supports main link and RSDS/mini-LVDS pin swapping for top or bottom mounting PCBs
  • LCD power sequence control
  • Supports fail-safe mode by scaling to VGA (640×480, 60Hz)
  • Supports programmable video pattern generation
  • Light sensor input and programmable Pulse-Width-Modulation backlight control output
  • Low bandwidth ADC for up to 16-button inputs
  • Slave I2C interface for chip control
  • I2C masters for expansion function
  • 100-pin TQFP RoHS Package

Applications

  • Direct Drive LCD Monitor
  • Notebook LCD panels
  • Embedded LCD panels